Silicon-on-Insulator (SOI) wafers are used for the fabrication of some integrated circuits. An SOI wafer comprises a relatively thick semiconductor substrate or handle wafer, an insulating layer (buried oxide layer) disposed on top of the substrate, and a relatively thin semiconductor layer (SOI layer) disposed on top of the insulating layer. The insulating layer most often comprises silicon dioxide with a thickness in the range of 0.1 to 3.0 microns. The SOI layer is usually single-crystal silicon with a thickness in the range of 0.1 to 25 microns.
The SOI layer typically has a certain conductivity provided by doping the SOI layer with impurities of a given species and doping concentration. The SOI doping is usually the lowest doping required for one of the layers that is used to form the semiconductor devices in the SOI layer. Other device layers are formed by adding more dopant to certain regions of the SOI layer, the additional dopant overwhelming the background doping of the SOI layer. In a typical SOI CMOS process, for example, an Nwell region and a Pwell region may be formed in the SOI layer by introducing N-type and P-type dopants, respectively. Using conventional doping techniques, the well regions are diffused down from the surface of the SOI layer, such that they have their maximum doping concentration near the SOI layer surface, and have some vertical extent (junction depth) in the SOI layer. Typical junction depths for these well regions may be in the range of 1.0 to 5.0 microns. If the SOI layer thickness is less than the junction depth, then the well region extends down to the interface of the SOI layer and the buried oxide layer.
During normal operation, semiconductor devices formed in SOI layers are subject to potential differences between the well regions and the underlying semiconductor substrate. The substrate is typically biased to the lowest potential of the IC, while the well regions are biased to potentials that are the same or higher. If a Pwell is in contact with the top of the buried oxide layer, then the presence of this potential difference will cause an accumulation layer of holes to form in the Pwell at the interface of the SOI layer and buried oxide layer. If an Nwell is in contact with the top of the buried oxide layer, then the presence of this potential difference will cause an depletion layer to form in the Nwell, starting at the interface of the SOI layer and buried oxide layer and extending upward into the Nwell. Such depletion of an Nwell formed in an SOI layer can cause problems with circuit operation due to parasitic effects.